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Low Voltage 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translator ADG3300
FEATURES
Bidirectional level translation Operates from 1.15 V to 5.5 V Low quiescent current <1 A No direction pin
FUNCTIONAL BLOCK DIAGRAM
VCCA VCCY
A1 A2
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
APPLICATIONS
Low voltage ASIC level translation Smart card readers Cell phones and cell phone cradles Portable communications devices Telecommunications equipment Network switches and routers Storage systems (SAN/NAS) Computing/server applications GPS Portable POS systems Low cost serial interfaces
A3 A4 A5 A6 A7 A8 EN GND
Figure 1.
GENERAL DESCRIPTION
The ADG3300 is a bidirectional logic level translator that contains eight bidirectional channels. It can be used in multivoltage digital system applications such as data transfer between a low voltage DSP/controller and a higher voltage device. The internal architecture allows the device to perform bidirectional logic level translation without an additional signal to set the direction of the translation. The voltage applied to VCCA sets the logic levels on the A side of the device, while VCCY sets the levels on the Y side. For proper operation, VCCA must always be less than VCCY. The VCCA-compatible logic signals applied to the A side of the device appear as VCCY-compatible levels on the Y side. Similarly, VCCY-compatible logic levels applied to the Y side of the device appear as VCCAcompatible logic levels on the A side. The enable pin provides three-state operation of the Y side pins. When the enable pin (EN) is pulled low, the A1 to A8 pins are internally pulled down by 6 k resistors, while the Y terminals are in the high impedance state. The EN pin is referred to VCCA supply voltage and driven high for normal operation. The ADG3300 is available in a compact 20-lead TSSOP package, and it is guaranteed to operate over the 1.15 V to 5.5 V supply voltage range and extended -40C to +85C temperature range.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. Bidirectional level translation. Fully guaranteed over the 1.15 V to 5.5 V supply range. No direction pin. 20-lead TSSOP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
05061-001
ADG3300
TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Test Circuits..................................................................................... 12 Terminology .................................................................................... 14 Theory of Operation ...................................................................... 15 Level Translator Architecture.................................................... 15 Input Driving Requirements..................................................... 15 Output Load Requirements ...................................................... 15 Enable Operation ....................................................................... 15 Power Supplies............................................................................ 15 Data Rate ..................................................................................... 16 Applications..................................................................................... 17 Layout Guidelines....................................................................... 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18
REVISION HISTORY
4/05--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG3300 SPECIFICATIONS1
VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. Table 1.
Parameter LOGIC INPUTS/OUTPUTS A Side Input High Voltage3 Input Low Voltage3 Output High Voltage Output Low Voltage Three-State Pull-Down Resistance Y Side Input Low Voltage3 Input High Voltage3 Output High Voltage Output Low Voltage Capacitance3 Leakage Current Enable (EN) Input High Voltage3 Input Low Voltage3 Leakage Current Capacitance3 Enable Time3 SWITCHING CHARACTERISTICS3 3.3 V 0.3 V VCCA VCCY, VCCY = 5 V 0.5 V A Y Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y A Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 1.8 V 0.15 V VCCA VCCY, VCCY = 3.3 V 0.3 V A Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Symbol Conditions Min Typ2 Max Unit
VIHA VIHA VILA VOHA VOLA RA,HiZ VIHY VILY VOHY VOLY CY ILY, HiZ VIHEN VIHEN VILEN ILEN CEN tEN
VCCA = 1.15 V VCCA = 1.2 V to 5.5 V VY = VCCY, IOH = 20 A, Figure 27 VY = 0 V, IOL = 20 A, Figure 27 EN = 0
VCCA - 0.3 VCCA - 0.4 0.4 VCCA - 0.4 4.2 VCCY - 0.4 0.4 6 0.4 8.4
V V V V V k V V V V pF A V V V A pF s
VA = VCCA, IOH = 20 A, Figure 28 VA = 0 V, IOL = 20 A, Figure 28 f = 1 MHz, EN = 0, Figure 31 VY = 0 V/VCCY, EN = 0, Figure 29 VCCA = 1.15 V VCCA = 1.2 V to 5.5 V VEN = 0 V/VCCA, VA = 0 V, Figure 30 RS = RT = 50 , VA = 0 V/VCCA (A Y), Figure 32
VCCY - 0.4 0.4 6 1 VCCA - 0.3 VCCA - 0.4 0.4 1 3 1 1.8
RS = RT = 50 , CL = 50 pF, Figure 33 tP, A-Y tR, A-Y tF, A-Y DMAX, A-Y tSKEW, A-Y tPPSKEW, A-Y RS = RT = 50 , CL = 15 pF, Figure 34 tP, Y-A tR, Y-A tF, Y-A DMAX, Y-A tSKEW, Y-A tPPSKEW, Y-A RS = RT = 50 , CL = 50 pF, Figure 33 tP, A-Y tR, A-Y tF, A-Y DMAX, A-Y tSKEW, A-Y tPPSKEW, A-Y 8 2 2 50 2 4 4 11 5 5 ns ns ns Mbps ns ns 50 2 3.5 2 4 1 3 7 3 7 ns ns ns Mbps ns ns 6 2 2 50 2 4 3 10 3.5 3.5 ns ns ns Mbps ns ns
Rev. 0 | Page 3 of 20
ADG3300
Parameter Y A Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 1.15 V to 1.3 V VCCA VCCY, VCCY = 3.3 V 0.3 V A Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y A Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 1.15 V to 1.3 V VCCA VCCY, VCCY = 1.8 V 0.3 V A Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y A Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 2.5 V 0.2 V VCCA VCCY, VCCY = 3.3 V 0.3 V A Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y A Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Symbol tP, Y-A tR, Y-A tF, Y-A DMAX, Y-A tSKEW, Y-A tPPSKEW, Y-A RS = RT = 50 , CL = 50 pF, Figure 33 tP, A-Y tR, A-Y tF, A-Y DMAX, A-Y tSKEW, A-Y tPPSKEW, A-Y RS = RT = 50 , CL = 15 pF, Figure 34 tP, Y-A tR, Y-A tF, Y-A DMAX, Y-A tSKEW, Y-A tPPSKEW, Y-A RS = RT = 50 , CL = 50 pF, Figure 33 tP, A-Y tR, A-Y tF, A-Y DMAX, A-Y tSKEW, A-Y tPPSKEW, A-Y RS = RT = 50 , CL = 15 pF, Figure 34 tP, Y-A tR, Y-A tF, Y-A DMAX, Y-A tSKEW, Y-A tPPSKEW, Y-A RS = RT = 50 , CL = 50 pF, Figure 33 tP, A-Y tR, A-Y tF, A-Y DMAX, A-Y tSKEW, A-Y tPPSKEW, A-Y RS = RT = 50 , CL = 15 pF, Figure 34 tP, Y-A tR, Y-A tF, Y-A DMAX, Y-A tSKEW, Y-A tPPSKEW, Y-A
Rev. 0 | Page 4 of 20
Conditions RS = RT = 50 , CL = 15 pF, Figure 34
Min
Typ2 5 2 2
Max 8 3.5 3.5 3 3
Unit ns ns ns Mbps ns ns
50 2
9 3 2 40 2
18 5 5 5 10 9 4 4 4 4
ns ns ns Mbps ns ns ns ns ns Mbps ns ns
5 2 2 40 2
12 7 3 25 2
25 12 5 5 15 35 16 6.5 6.5 23.5
ns ns ns Mbps ns ns ns ns ns Mbps ns ns
14 5 2.5 25 3
7 2.5 2 60 1.5
10 4 5 2 4 8 4 5 3 3
ns ns ns Mbps ns ns ns ns ns Mbps ns ns
5 1 3 60 2
ADG3300
Parameter POWER REQUIREMENTS Power Supply Voltages Quiescent Power Supply Current Symbol VCCA VCCY ICCA ICCY Three-State Mode Power Supply Current IHiZA IHiZY Conditions VCCA VCCY VA = 0 V/VCCA, VY = 0 V/VCCY, VCCA = VCCY = 5.5 V, EN = 1 VA = 0 V/VCCA, VY = 0 V/VCCY, VCCA = VCCY = 5.5 V, EN = 1 VCCA = VCCY = 5.5 V, EN = 0 VCCA = VCCY = 5.5 V, EN = 0 Min 1.15 1.65 0.17 0.27 0.1 0.1 Typ2 Max 5.5 5.5 5 5 5 5 Unit V V A A A A
1 2
Temperature range is a follows: B version: -40C to +85C. All typical values are at TA = 25C, unless otherwise noted. 3 Guaranteed by design; not subject to production test.
Rev. 0 | Page 5 of 20
ADG3300 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 2.
Parameter VCCA to GND VCCY to GND Digtal Inputs (A) Digtal Inputs (Y) EN to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature JA Thermal Impedance (4-Layer Board) 20-Lead TSSOP Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (<20 sec) Rating -0.3 V to +7 V VCCA to +7 V -0.3 V to (VCCA + 0.3 V) -0.3 V to (VCCY + 0.3 V) -0.3 V to +7 V -40C to +85C -65C to +150C 150C 78C/W 300C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 6 of 20
ADG3300 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A1 VCCA A2 A3 A4 A5 A6
1 2 3
20 Y1 19 VCCY
ADG3300
4 5 6 7
18 Y2 17 Y3 16 Y4 15 Y5 14 Y6 13 Y7
05061-002
TOP VIEW (Not to Scale)
A7 8 A8
9
12 Y8 11 GND
EN 10
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic A1 VCCA A2 A3 A4 A5 A6 A7 A8 EN GND Y8 Y7 Y6 Y5 Y4 Y3 Y2 VCCY Y1 Description Input/Output A1. Referenced to VCCA. Power Supply Voltage Input for the A1 to A8 I/O pins (1.15 V VCCA < VCCY). Input/Output A2. Referenced to VCCA. Input/Output A3. Referenced to VCCA. Input/Output A4. Referenced to VCCA. Input/Output A5. Referenced to VCCA. Input/Output A6. Referenced to VCCA. Input/Output A7. Referenced to VCCA. Input/Output A8. Referenced to VCCA. Active High Enable Input. Ground. Input/Output Y8. Referenced to VCCY. Input/Output Y7. Referenced to VCCY. Input/Output Y6. Referenced to VCCY. Input/Output Y5. Referenced to VCCY. Input/Output Y4. Referenced to VCCY. Input/Output Y3. Referenced to VCCY. Input/Output Y2. Referenced to VCCY. Power Supply Voltage Input for the Y1 to Y8 I/O pins (1.65 V VCCY 5.5 V). Input/Output Y1. Referenced to VCCY.
Rev. 0 | Page 7 of 20
ADG3300 TYPICAL PERFORMANCE CHARACTERISTICS
1.0
3.0
TA = 25C 1 CHANNEL 0.9 CL = 50pF 0.8 0.7
ICCA (mA)
2.5
TA = 25C 1 CHANNEL CL = 15pF
VCCA = 3.3V, VCCY = 5V
2.0
0.6 0.5 0.4 0.3 0.2 0.1 VCCA = 1.2V, VCCY = 1.8V 0
05061-003
ICCY (mA)
VCCA = 3.3V, VCCY = 5V 1.5
VCCA = 1.8V, VCCY = 3.3V
1.0 VCCA = 1.8V, VCCY = 3.3V 0.5 VCCA = 1.2V, VCCY = 1.8V
0
5
10
15
20 25 30 35 DATA RATE (Mbps)
40
45
50
0
5
10
15
20
25
30
35
40
45
50
DATA RATE (Mbps)
Figure 3. ICCA vs. Data Rate (A Y Level Translation)
10
1.6 1.4 1.2
Figure 6. ICCY vs. Data Rate (Y A Level Translation)
TA = 25C 1 CHANNEL 9 CL = 50pF 8 7 VCCA = 3.3V, VCCY = 5V
TA = 25C 1 CHANNEL VCCA = 1.2V VCCY = 1.8V
20Mbps
ICCY (mA)
6 5 4 3 2 1 0 0 5 10 15 VCCA = 1.2V, VCCY = 1.8V
05061-004
ICCY (mA)
1.0 0.8 10Mbps 0.6
VCCA = 1.8V, VCCY = 3.3V
0.4 0.2 1Mbps
05061-007
5Mbps
0
20 25 30 35 DATA RATE (Mbps)
40
45
50
13
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
Figure 4. ICCY vs. Data Rate (A Y Level Translation)
3.0
Figure 7. ICCY vs. Capacitive Load at Pin Y for A Y (1.2 V 1.8 V) Level Translation
1.0 0.9 0.8 TA = 25C 1 CHANNEL VCCA = 1.2V VCCY =1.8V
2.5
TA = 25C 1 CHANNEL CL = 15pF VCCA = 3.3V, VCCY = 5V
2.0
0.7
ICCA (mA)
ICCA (mA)
0.6 20Mbps 0.5 0.4 0.3
1.5
1.0 VCCA = 1.8V, VCCY = 3.3V 0.5
0.2
VCCA = 1.2V, VCCY = 1.8V
05061-005
10Mbps 5Mbps 1Mbps 13 23 33 43 CAPACITIVE LOAD (pF) 53
05061-008
0.1
45 50
0
0
5
10
15
20
25
30
35
40
0
DATA RATE (Mbps)
Figure 5. ICCA vs. Data Rate (Y A Level Translation)
Figure 8. ICCA vs. Capacitive Load at Pin A for Y A (1.8 V 1.2 V) Level Translation
Rev. 0 | Page 8 of 20
05061-006
0
ADG3300
9 8 7 6
ICCY (mA)
ICCA (mA)
TA = 25C 1 CHANNEL VCCA = 1.8V VCCY = 3.3V 50Mbps
7 TA = 25C 1 CHANNEL 6 VCCA = 3.3V VCCY = 5V 5
50Mbps
5 4 3 2
10Mbps 30Mbps
4
3 30Mbps 20Mbps
20Mbps
2
10Mbps 1 5Mbps
05061-009
1 0 13
5Mbps 23 33 43 53 CAPACITIVE LOAD (pF) 63 73
23
33 CAPACITIVE LOAD (pF)
43
53
Figure 9. ICCY vs. Capacitive Load at Pin Y for A Y (1.8 V 3.3 V) Level Translation
5.0 4.5 4.0 3.5
ICCA (mA)
TA = 25C 1 CHANNEL VCCA = 1.8V VCCY = 3.3V
Figure 12. ICCA vs. Capacitive Load at Pin A for Y A (5 V 3.3 V) Level Translation
10 TA = 25C 9 1 CHANNEL DATA RATE = 50kbps 8 7
VCCA = 1.2V, VCCY = 1.8V
3.0 2.5 2.0 1.5
RISE TIME (ns)
50Mbps
6 5 4 3 VCCA = 1.8V, VCCY = 3.3V
30Mbps 20Mbps
1.0
10Mbps
2 VCCA = 3.3V, VCCY = 5V 1
23 33 43 CAPACITIVE LOAD (pF) 53
05061-010
0.5 0 13
5Mbps
23
33 43 53 CAPACITIVE LOAD (pF)
63
73
Figure 10. ICCA vs. Capacitive Load at Pin A for Y A (3.3 V 1.8 V) Level Translation
12
Figure 13. Rise Time vs. Capacitive Load at Pin Y (A Y Level Translation)
TA = 25C 1 CHANNEL VCCA = 3.3V 10 V CCY = 5V
4.0
50Mbps
TA = 25C 1 CHANNEL 3.5 DATA RATE = 50kbps 3.0
VCCA = 1.2V, VCCY = 1.8V
8
FALL TIME (ns)
2.5 VCCA = 1.8V, VCCY = 3.3V 2.0 1.5 VCCA = 3.3V, VCCY = 5V 1.0 0.5
ICCY (mA)
30Mbps 6 20Mbps 4 10Mbps 2 5Mbps
05061-011
23
33
43
53
63
73
13
23
CAPACITIVE LOAD (pF)
33 43 53 CAPACITIVE LOAD (pF)
63
73
Figure 11. ICCY vs. Capacitive Load at Pin Y for A Y (3.3 V 5 V) Level Translation
Figure 14. Fall Time vs. Capacitive Load at Pin Y (A Y Level Translation)
Rev. 0 | Page 9 of 20
05061-014
0 13
0
05061-013
0 13
05061-012
0 13
ADG3300
10 TA = 25C 9 1 CHANNEL DATA RATE = 50kbps 8 7 12 DATA RATE = 50kbps TA = 25C 1 CHANNEL VCCA = 1.2V, VCCY = 1.8V
10
PROPAGATION DELAY (ns)
RISE TIME (ns)
VCCA = 1.2V, VCCY = 1.8V
8
6 5 4 3 2 1 0 13 VCCA = 3.3V, VCCY = 5V
05061-015
6 VCCA = 1.8V, VCCY = 3.3V 4
VCCA = 1.8V, VCCY = 3.3V
2
VCCA = 3.3V, VCCY = 5V
18
23
28
33
38
43
48
53
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 15. Rise Time vs. Capacitive Load at Pin A (Y A Level Translation)
Figure 18. Propagation Delay (tPHL) vs. Capacitive Load at Pin Y (A Y Level Translation)
9
4.0 3.5 3.0 TA = 25C 1 CHANNEL DATA RATE = 50kbps
8
TA = 25C 1 CHANNEL DATA RATE = 50kbps VCCA = 1.2V, VCCY = 1.8V
PROPAGATION DELAY (ns)
7 6 5 4 3 VCCA = 1.8V, VCCY = 3.3V 2 1
FALL TIME (ns)
2.5 VCCA = 1.2V, VCCY = 1.8V 2.0 1.5 1.0 0.5
05061-016
VCCA = 1.8V, VCCY = 3.3V
VCCA = 3.3V, VCCY = 5V
VCCA = 3.3V, VCCY = 5V
05061-019 05061-020
0 13 18 23 28 33 38 43 CAPACITIVE LOAD (pF) 48 53
0 13
18
23
28
33
38
43
48
53
CAPACITIVE LOAD (pF)
Figure 16. Fall Time vs. Capacitive Load at Pin A (Y A Level Translation)
Figure 19. Propagation Delay (tPLH) vs. Capacitive Load at Pin A (Y A Level Translation)
9
14 TA = 25C 1 CHANNEL 12 DATA RATE = 50kbps
PROPAGATION DELAY (ns)
TA = 25C 1 CHANNEL 8 DATA RATE = 50kbps
10
PROPAGATION DELAY (ns)
VCCA = 1.2V, VCCY = 1.8V
7 6 5 4 3 2 1
VCCA = 1.2V, VCCY = 1.8V
8
6
VCCA = 1.8V, VCCY = 3.3V
VCCA = 1.8V, VCCY = 3.3V VCCA = 3.3V, VCCY = 5V
4 VCCA = 3.3V, VCCY = 5V 2
05061-017
0 13
0 13 18 23 28 33 38 43 CAPACITIVE LOAD (pF) 48 53
23
33 43 53 CAPACITIVE LOAD (pF)
63
73
Figure 17. Propagation Delay (tPLH) vs. Capacitive Load at Pin Y (A Y Level Translation)
Figure 20. Propagation Delay(tPHL) vs. Capacitive Load at Pin A (Y A Level Translation)
Rev. 0 | Page 10 of 20
05061-018
0 13
ADG3300
TA = 25C DATA RATE = 25Mbps CL = 50pF 1 CHANNEL TA = 25C DATA RATE = 50Mbps CL = 15pF 1 CHANNEL
05061-021
200mV/DIV
5ns/DIV
400mV/DIV
3ns/DIV
Figure 21. Eye Diagram at Y Output (1.2 V to 1.8 V Level Translation, 25 Mbps)
Figure 24. Eye Diagram at A Output (3.3 V to 1.8 V Level Translation, 50 Mbps)
TA = 25C DATA RATE = 25Mbps CL = 50pF 1 CHANNEL
TA = 25C DATA RATE = 50Mbps CL = 50pF 1 CHANNEL
400mV/DIV
5ns/DIV
05061-022
1V/DIV
3ns/DIV
Figure 22. Eye Diagram at A Output (1.8 V to 1.2 V Level Translation, 25 Mbps)
Figure 25. Eye Diagram at Y Output (3.3 V to 5 V Level Translation, 50 Mbps)
TA = 25C DATA RATE = 50Mbps
CL = 50pF 1 CHANNEL
TA = 25C DATA RATE = 50Mbps CL = 15pF 1 CHANNEL
05061-023
500mV/DIV
3ns/DIV
800mV/DIV
3ns/DIV
Figure 23. Eye Diagram at Y Output (1.8 V to 3.3 V Level Translation, 50 Mbps)
Figure 26. Eye Diagram at A Output (5 V to 3.3 V Level Translation, 50 Mbps)
Rev. 0 | Page 11 of 20
05061-026
05061-025
05061-024
ADG3300 TEST CIRCUITS
EN VCCA 0.1F
ADG3300
VCCY 0.1F
VCCA
A Y K2 K1 GND
ADG3300
VCCY 0.1F
0.1F
A
Y
IOH
IOL
05061-027
A K
EN GND
05061-031
Figure 27. VOH/VOL Voltages at Pin A
Figure 30. EN Pin Leakage Current
EN VCCA 0.1F
ADG3300
VCCY 0.1F
EN VCCA
ADG3300
VCCY
K2
A
Y
A
K1
Y CAPACITANCE METER
05061-033
GND
GND
IOH IOL
05061-028
Figure 31.Capacitance at Pin Y
Figure 28. VOH/VOL Voltages at Pin Y
EN VCCA 0.1F
ADG3300
VCCY 0.1F
A
Y
K A
Figure 29. Three-State Leakage Current at Pin Y
Rev. 0 | Page 12 of 20
05061-030
GND
ADG3300
VCCA 0.1F + 10F
ADG3300
VCCY 0.1F + 10F 1M
K1
VA
A
Y 50pF
VY
K2 1M
SIGNAL SOURCE EN RS 50 Z0 = 50 VEN RT 50 GND
VEN
tEN1
VCCA 0V VCCA
VA 90% VY 0V VCCY 0V VCCA 0V VCCA 0V VCCY
05061-034
VEN VA
tEN2
VY 10% NOTES
0V
1. tEN IS WHICHEVER IS LARGER BETWEEN tEN1 AND tEN2.
Figure 32. Enable Time
EN VCCA SIGNAL SOURCE RS 50 0.1F Z0 = 50 V A RT 50 + 10F
ADG3300
VCCY 0.1F + 10F
0.1F EN VCCA + 10F A
ADG3300
VCCY 0.1F + 10F SIGNAL SOURCE Y VY RT 50 Z0 = 50 RS 50
A
Y
VY 50pF
VA 15pF
GND
GND
VA 50%
50%
VY
tP,A-Y
VY 90% 50% 10%
tP,A-Y
VA 90% 50% 10%
05061-035
tP,Y-A
tP,Y-A
tF,A-Y
tR,A-Y
tF,Y-A
tR,Y-A
Figure 33. Switching Characteristics (A Y Level Translation)
Figure 34. Switching Characteristics (Y A Level Translation)
Rev. 0 | Page 13 of 20
05061-036
ADG3300 TERMINOLOGY
Table 4.
Symbol VIHA VILA VOHA VOLA RA,HiZ VIHY VILY VOHY VOLY CY ILY, HiZ VIHEN VILEN CEN ILEN tEN tP, A-Y tR, A-Y tF, A-Y DMAX, A-Y tSKEW, A-Y tPPSKEW, A-Y tP, Y-A tR, Y-A tF, Y-A DMAX, Y-A tSKEW, Y-A tPPSKEW, Y-A VCCA VCCY ICCA ICCY IHiZA IHiZY Description Logic input high voltage at Pins A1 to A8. Logic input low voltage at Pins A1 to A8. Logic output high voltage at Pins A1 to A8. Logic output low voltage at Pins A1 to A8. Pull-down resistance measured at Pins A1 to A8 when EN = 0. Logic input high voltage at Pins Y1 to Y8. Logic input low voltage at Pins Y1 to Y8. Logic output high voltage at Pins Y1 to Y8. Logic output low voltage at Pins Y1 to Y8. Capacitance measured at Pins Y1 to Y8 (EN = 0). Leakage current at Pins Y1 to Y8 when EN = 0 (high impedance state at Pins Y1 to Y8). Logic input high voltage at the EN pin. Logic input low voltage at the EN pin. Capacitance measured at EN pin. Enable (EN) pin leakage curent. Three-state enable time for Pins Y1 to Y8. Propagation delay when translating logic levels in the A Y direction. Rise time when translating logic levels in the A Y direction. Fall time when translating logic levels in the A Y direction. Guaranteed data rate when translating logic levels in the A Y direction under the driving and loading conditions specified in Table 1. Difference between propagation delays on any two channels when translating logic levels in the A Y direction. Difference in propagation delay between any one channel and the same channel on a different part (under the same driving/loading conditions) when translating logic levels in the A Y direction. Propagation delay when translating logic levels in the Y A direction. Rise time when translating logic levels in the Y A direction. Fall time when translating logic levels in the Y A direction. Guaranteed data rate when translating logic levels in the Y A direction under the driving and loading conditions specified in Table 1. Difference between propagation delays on any two channels when translating logic levels in the Y A direction. Difference in propagation delay between any one channel and the same channel on a different part (under the same driving/loading conditions) when translating in the Y A direction. VCCA supply voltage. VCCY supply voltage. VCCA supply current. VCCY supply current. VCCA supply current during three-state mode (EN = 0). VCCY supply current during three-state mode (EN = 0).
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ADG3300 THEORY OF OPERATION
The ADG3300 level translator allows the level shifting necessary for data transfer in a system where multiple supply voltages are used. The device requires two supplies, VCCA and VCCY (VCCA VCCY). These supplies set the logic levels on each side of the device. When driving the A pins, the device translates the VCCAcompatible logic levels to VCCY-compatible logic levels available at the Y pins. Similarly, since the device is capable of bidirectional translation, when driving the Y pins, the VCCY-compatible logic levels are translated to VCCA-compatible logic levels available at the A pins. When EN = 0, the A1 to A8 are internally pulled down with 6 k resistors while Y1 to Y8 pins are three-stated. When EN is driven high, the ADG3300 goes into normal operation mode and performs level translation.
INPUT DRIVING REQUIREMENTS
To ensure correct operation of the ADG3300, the circuit that drives the input of an ADG3300 channels should have an output impedance of less than or equal to 150 and a minimum current driving capability of 36 mA.
OUTPUT LOAD REQUIREMENTS
The ADG3300 level translator is designed to drive CMOScompatible loads. If current driving capability is required, it is recommended to use buffers between the ADG3300 outputs and the load.
ENABLE OPERATION
The ADG3300 provides three-state operation at the Y I/O pins by using the enable (EN) pin as shown in Table 5. Table 5. Truth Table
EN 0 1
1 2
LEVEL TRANSLATOR ARCHITECTURE
The ADG3300 consists of eight bidirectional channels. Each channel can translate logic levels in either the A Y or the Y A direction. It uses a one-shot accelerator architecture, which ensures excellent switching characteristics. Figure 35 shows a simplified block diagram of a bidirectional channel.
VCCA VCCY
Y I/O Pins Hi-Z1 Normal operation2
A I/O Pins 6 k pull-down to GND Normal operation2
High impedance state. In normal operation, the ADG3300 performs level translation.
T1 6k U1 U2
T2
A
P
ONE-SHOT GENERATOR
N
Y
When EN = 0, the ADG3300 enters into three-state mode. In this mode the current consumption from both the VCCA and VCCY supplies is reduced, allowing the user to save power, which is critical, especially for battery-operated systems. The EN input pin can be driven with either VCCA- or VCCY-compatible logic levels.
POWER SUPPLIES
6k U4 U3
Figure 35. Simplified Block Diagram of an ADG3300 Channel
The logic level translation in the A Y direction is performed using a level translator (U1) and an inverter (U2), and the translation in the Y A direction is performed using the inverters U3 and U4. The one-shot generator detects a rising or falling edge present on either the A side or the Y side of the channel. It sends a short pulse that turns on the PMOS transistors (T1-T2) for a rising edge, or the NMOS transistors (T3-T4) for a falling edge. This charges/discharges the capacitive load faster, which results in fast rise and fall times. The inputs of the unused channels (A or Y) should be tied to their corresponding VCC rail (VCCA or VCCY) or to GND.
05061-037
T4
T3
For proper operation of the ADG3300, the voltage applied to the VCCA must always be less than or equal to the voltage applied to VCCY. To meet this condition, the recommended power-up sequence is VCCY first and then VCCA. The ADG3300 operates properly only after both supply voltages reach their nominal values. It is not recommended to use the part in a system where VCCA might be greater than VCCY during power-up due to a significant increase in the current taken from the VCCA supply. For optimum performance, the VCCA and VCCY pins should be decoupled to GND as close as possible to the device.
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ADG3300
DATA RATE
The maximum data rate at which the device is guaranteed to operate is a function of the VCCA and VCCY supply voltage combination and the load capacitance. It is given by the maximum frequency of a square wave that can be applied to the device, which meets the VOH and VOL levels at the output and does not exceed the maximum junction temperature (see Table 2). Table 6 shows the guaranteed data rates at which the ADG3300 can operate in both directions (A Y and Y A level translation) for various VCCA and VCCY supply combinations.
Table 6. Guaranteed Data Rate (Mbps)1
VCCY VCCA 1.2 V (1.15 V to 1.3 V) 1.8 V (1.65 V to 1.95 V) 2.5 V (2.3 V to 2.7 V) 3.3 V (3.0 V to 3.6 V) 5 V (4.5 V to 5.5 V)
1
1.8 V (1.65 V to 1.95 V) 25 -
2.5 V (2.3 V to 2.7 V) 30 45 -
3.3 V (3.0 V to 3.6 V) 40 50 60 -
5V (4.5 V to 5.5 V) 40 50 50 50 -
The load capacitance used is 50 pF when translating in the A Y direction and 15 pF when translating in the Y A direction.
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ADG3300 APPLICATIONS
The ADG3300 is designed for digital circuits that operate at different supply voltages; therefore, logic level translation is required. The lower voltage logic signals are connected to the A pins, and the higher voltage logic signals are connected to the Y pins. The ADG3300 can provide level translation in both directions from A Y and Y A on all eight channels, eliminating the need for a level translator IC for each direction. The internal architecture allows the ADG3300 to perform bidirectional level translation without an additional signal to set the direction of the translation. It also allows simultaneous data flow in both directions on the same part, for example, four channels translate in the A Y direction while the other four translate in the Y A direction. This simplifies the design by eliminating the timing requirements for the direction signal and reduces the number of ICs used for level translation. Figure 36 shows an application where a 1.8 V microprocessor can read or write data to or from a 3.3 V peripheral device using an 8-bit bus.
100nF 100nF
other devices without causing contention issues. Figure 37 shows an application where a 3.3 V microprocessor is connected to 1.8 V peripheral devices using the three-state feature.
100nF 100nF
3.3V
I/OH1
Y1 VCCY
A1 VCCA A2
I/OL1
1.8V
I/OH2 I/OH3 MICROPROCESSOR/ I/OH4 MICROCONTROLLER/ I/OH5 DSP I/OH6 I/OH7 I/OH8 GND CS
Y2 Y3 Y4 Y5 Y6 Y7 Y8 GND
I/OL 2 I/OL 3 I/OL 4 I/OL 5 I/OL 6 I/OL 7 I/OL 8 GND PERIPHERAL DEVICE 1
ADG3300
A3 A4 A5 A6 A7 A8 EN
100nF
100nF
Y1 VCCY Y2 Y3 Y4 Y5 Y6 Y7
A1 VCCA A2
I/OL 1
1.8V
I/OL 2 I/OL 3 I/OL 4 I/OL 5 I/OL 6 I/OL 7 I/OL 8 GND
05061-039
ADG3300
A3 A4 A5 A6 A7 A8 EN
PERIPHERAL DEVICE 2
1.8V
I/OL1
A1 VCCA A2
Y1 VCCY
I/OH1
3.3V
Y8 GND
I/OL2 I/OL3 MICROPROCESSOR/ I/OL4 MICROCONTROLLER/ DSP I/OL5
Y2
I/OH2
A3
Y3
I/OH3
Figure 37. 1.8 V to 3.3 V Level Translation Circuit Using the Three-State Feature
PERIPHERAL DEVICE
A4
Y4
I/OH4 I/OH5
ADG3300
A5 Y5
LAYOUT GUIDELINES
As with any high speed digital IC, the printed circuit board layout is important in the overall circuit performance. Care should be taken to ensure proper power supply bypass and return paths for the high speed signals. Each VCC pin (VCCA and VCCY) should be bypassed using low effective series resistance (ESR) and effective series inductance (ESI) capacitors placed as close as possible to the VCCA and VCCY pins. The parasitic inductance of the high speed signal track might cause significant overshoot. This effect can be reduced by keeping the length of the tracks as short as possible. A solid copper plane for the return path (GND) is also recommended.
I/OL6 I/OL7 I/OL8
A6
Y6
I/OH6
A7
Y7
I/OH7
A8
Y8
I/OH8 GND
GND
EN
GND
Figure 36. 1.8 V to 3.3 V 8-Bit Level Translation Circuit
When the application requires level translation between a microprocessor and multiple peripheral devices, the ADG3300 Y I/O pins (Y1 to Y8) can be three-stated by setting EN = 0. This feature allows the ADG3300 to share the data buses with
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05061-038
ADG3300 OUTLINE DIMENSIONS
6.60 6.50 6.40
20
11
4.50 4.40 4.30 6.40 BSC
1 10
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 0.20 0.09 8 0 0.75 0.60 0.45
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-153AC
Figure 38 . 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters
ORDERING GUIDE
Model ADG3300BRUZ1 ADG3300BRUZ-REEL1 ADG3300BRUZ-REEL71
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description TSSOP TSSOP TSSOP
Package Option RU-20 RU-20 RU-20
Z = Pb-free part.
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ADG3300 NOTES
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ADG3300 NOTES
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05061-0-4/05(0)
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